Method based on backboard transmitting time division multiplexing circuit data and a bridge connector

ABSTRACT

A method for multi-path TDM data transmission includes: applying a plurality of high-speed serial lines to connect a center switch network board to a plurality of service boards; multiplexing multi-path TDM data from the center switch network board at transmitting side, and transmitting TDM data multiplexed in batch via one of the high-speed serial lines to one of the service boards; at receiving side, serial receiving the TDM data multiplexed and de-multiplexing the TDM data multiplexed to multiple TDM paths. The TDM bridge connector includes: a TDM high-speed serial transmitting adaptive circuit, and a TDM high-speed serial receiving adaptive circuit and a clock control circuit. The invention increases greatly transmission capacity and looses the requirement of clock synchronization, so the system reliability is greatly raised.

FIELD OF THE TECHNOLOGY

The invention generally relates to the time division multiplexing (TDM)technology, specifically to a TDM data transmission method on thebackplane and a TDM bridge connector thereof.

BACKGROUND OF THE INVENTION

Along with the differential signal level getting lower, noise immunityand transmission rate are getting higher, it is required that thetransmission capacity should be getting higher. Traditionally, the TDMcentralized switching structure is shown in FIG. 1, where every serviceboard shares the TDM bus 12, and the center switch network boarddistributes clock, for data transmission at backplane circuit, to eachservice board with a point-to-point mode or a bus mode.

Suppose that clock high-level duration is t, data is transmitted atleading edge of the clock and is sampled at falling edge of the clock,then the time sequence difference of the traditional synchronous datatransmission based on backplane is shown in FIG. 2, where phase betweenthe frame synchronization signal and the clock is not aligned. As shownin FIG. 2 the frame synchronization signal between the center switchnetwork board and the service boards has to time delay and so does theclock between the center switch network board and the service boards,transmission time for data from the center switch network board to theservice boards is t₂=t+t₀ and transmission time for data from theservice boards to the center switch network board is only t₁=t−t₀.Obviously, the transmission time is asymmetric, and when thetransmission frequency is very high, the system reliability is greatlyreduced, which means that the system capacity cannot be furtherincreased. Therefore, clock synchronization is a bottleneck oftraditional data transmission based on backplane bus with strictsynchronization.

Since the distance and distributed parameters between different slots ofthe backplane are different, the time delay for different slots isdifferent. There are disadvantages for the bus mode of signaltransmission: a large area, a long distance, many slots, density pins,serious switching noise and electromagnetic interference (EMI) etc.,when they are not dealt with adequately, there will be serious signalreflection and interference that cause signal distortion. In this case,the transmission rate is limited for the system reliability.

In order to increase transmission capacity of backplane circuit,increasing number of transmission signals is a fundamental method, butthis is implemented at a cost of a complex system structure, reliabilityand performance, and the number of transmission signals is limited.

In summary, the disadvantages of traditional TDM bus data transmissionbased on backplane is as following:

1) it requires strict synchronization, i.e. phase between the framesignal and clock signal should be aligned more strictly;

2) There are disadvantages for the bus mode of signal transmission: alarge area, a long distance, many slots, density pins, serious switchingnoise and electromagnetic interference (EMI) etc. Strict synchronizationis very difficult. The transmission rate is greatly limited in order toguarantee system reliability;

3) no matter whether the clock signal is distributed with point-to-pointmode or bus mode, since the distance and distributed parameters betweendifferent slots are different, the time delay is different;

4) In order to increase transmission capacity of backplane circuit,increasing number of transmission signals is a fundamental method, butthis is implemented at a cost of a complex system structure, reliabilityand performance, and the number of transmission signals is limited.

SUMMARY OF THE INVENTION

Considering what have been mentioned above, the invention provides amethod for multi-path TDM data transmission based on backplane and abridge connector thereof in order to reduce synchronization requirementof the clock, increase transmission rate at the backplane circuit andswitching capacity, and raise data transmission quality and reliability.

A method for multi-path TDM data transmission includes:

applying a plurality of high-speed serial lines to connect the centerswitch network board with a plurality of service boards;

multi-path TDM data is multiplexed at the transmitting side, andtransmitted in batch to one of the service boards via one of thehigh-speed serial lines; at the receiving side, data are seriallyreceived and de-multiplexed to every TDM path.

According to the method, at the transmitting side, the multi-path TDMdata are multiplexed by taking a frame as a unit, and then transmittedin batch to said high-speed serial line on the backplane; at thereceiving side, data received by the high-speed serial line arede-multiplexed to every TDM paths by taking a frame as a unit; said dataserial transmitting and receiving takes the TDM clock as sampling clock.

According to the method, at the transmitting side, the multi-path TDMdata are multiplexed by taking a time-slot as a unit, and thentransmitted in batch to said high-speed serial line on the backplane; atthe receiving side, data received by the high-speed serial line arede-multiplexed to every TDM path by taking a time-slot as a unit; saiddata serial transmitting and receiving takes the TDM clock as samplingclock.

According to the method, at the transmitting side, the multi-path TDMdata are multiplexed by taking a bit as a unit, and then transmitted inbatch to said high-speed serial line on the backplane; at the receivingside, data received by the high-speed serial line are de-multiplexed toevery TDM path by taking a bit as a unit; said data serial transmittingand receiving takes n multiple of TDM clock as sampling clock, wherein nis an integer greater than zero.

The multiplexing of the multi-path TDM data, mentioned above, can alsobe done by a high-speed serial driver that makes parallel-to-serialconversion, and then sent to the high-speed serial line on the backplaneat the transmitting side; at the receiving side, the high-speed serialdriver synchronously receives the data and makes serial-to-parallelconversion to sample data for every TDM path according to the TDM framesynchronization.

According to the method, said TDM frame synchronization signal and clocksignal at the receiving side can be distributed by a point-to-point modeor a bus mode.

A method for implementing said TDM Bridge connector includes:

A TDM Bridge connector for multi-path TDM data transmission includes:

A TDM high-speed serial transmitting adaptive circuit, which connectswith the data signal of the TDM switching circuit and a plurality ofhigh-speed serial lines on the backplane, receives a multi-path TDM datafrom the TDM switching circuit, and after multiplexing the TDM datamultiplexed are sent to one of the service boards via one of thehigh-speed serial lines on the backplane;

A TDM high-speed serial receiving adaptive circuit, which connects withthe high-speed serial line on its receiving end and the data line of theTDM switching circuit on its transmitting end, serially receives theserial data sent from the high-speed serial line, and afterde-multiplexing they are sent to the TDM switching circuit;

-   -   And a clock control circuit, which is connected with the clock        and sync signal of the TDM switching circuit, provides clock and        sync signal.

According to the TDM bridge connector of the invention, said high-speedserial transmitting adaptive circuit further includes: a TDM receivinginterface that connects with the data signal of the TDM switchingcircuit to receive the multi-path TDM data; a store-and-forward circuitthat converts the received multi-path TDM data to one line serial data;a high-speed serial transmitting interface that connects with thehigh-speed serial line on the backplane to adapt and send the serialdata to the high-speed serial line; said high-speed serial receivingadaptive circuit further includes: a high-speed serial receivinginterface that connects with the high-speed serial line on the backplaneto receive the serial data from the high-speed serial line; astore-and-forward circuit that converts the received serial data tomulti-path TDM data; and a TDM transmitting interface that connects withthe TDM switching circuit for sending the TDM data to the TDM switchingcircuit.

According to the TDM bridge connector of the invention, said high-speedserial transmitting adaptive circuit further includes: a TDM receivinginterface that connects with the data signal of the TDM switchingcircuit to receive the multi-path TDM data; a parallel-to-serial circuitthat converts the received multi-path TDM data to one line serial data;a high-speed serial transmitting interface that connects with thehigh-speed serial line on the backplane to adapt and send the serialdata to the high-speed serial line; said high-speed serial receivingadaptive circuit further includes: a high-speed serial receivinginterface that connects with the high-speed serial line on the backplaneto receive the serial data from the high-speed serial line; aserial-to-parallel circuit that converts the received serial data tomulti-path TDM data; and a TDM transmitting interface that connects withthe TDM switching circuit for sending the TDM data to the TDM switchingcircuit.

Said high-speed serial transmitting adaptive circuit further includes aclock multiple frequency circuit that provides a multiple frequency ofthe clock signal acting as a clock for the high-speed serial datatransmission; said high-speed serial receiving adaptive circuit furtherincludes a multiple frequency of the clock signal as a clock for thehigh-speed serial data receiving.

Furthermore, the high-speed serial receiving adaptive circuit can alsoinclude a store-and-forward circuit; and the high-speed serialtransmitting adaptive circuit includes a clock multiple frequencycircuit that provides a multiple frequency of the TDM switching circuitclock signal as a clock signal for transmitting high-speed serial data.

Said high-speed serial line includes a downward transmission line fromthe center switch network board to the service boards and an upwardtransmission line from the service boards to the center switch networkboard.

Said high-speed serial line includes a TDM data sending line, a TDM datareceiving line, a TDM frame sync line and a clock line.

The invention takes a high-speed serial line on backplane to connect thecenter switch network board and every service board and to multiplex orinterleave/de-multiplex or de-interleave the multi-path TDM data fortransmission in batch; in this way, the transmission rate and switchingcapacity on backplane are greatly increased and at the same time theaccurate requirement of the transmission clock phase is decreased, andsource of signals on backplane is saved; in addition, because of usingthe differential transmission mode the noise interference and EMI arereduced. Consequently, data transmission quality and reliability of thesystem is greatly increased.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a diagram of the traditional TDM concentrated switchingstructure.

FIG. 2 shows a time delay of the traditional TDM clock concentrateddistributing.

FIG. 3 shows the diagram of a TDM concentrated switching with high-speedserial line.

FIG. 4 shows the diagram of a TDM switching with TDM bridge connector.

FIG. 5 shows an embodiment of the TDM bridge connector.

FIG. 6 shows the diagram of connection between the center switch networkboard and service boards in the FIG. 5 embodiment.

FIG. 7 shows a time sequence diagram for multi-path data transmissionwhen taking a frame as a unit.

FIG. 8 shows a time sequence diagram for multi-path data transmissionwhen taking a time-slot as a unit.

FIG. 9 shows the diagram of a high-speed serial driver.

FIG. 10 shows the diagram of connection between the center switchnetwork board and service boards in the FIG. 9 embodiment.

FIG. 11 shows a time sequence diagram of multi-path data transmission byusing synchronous multiplexing/de-multiplexing.

FIG. 12 shows the diagram of connection between the center switchnetwork board and service boards by using synchronous transmission andstore-and-forward for multi-path data transmission.

FIG. 13 shows the diagram of connection between the center switchnetwork board and service boards by using synchronous transmission andstore-and-forward for multi-path data transmission and adding a clockdouble frequency circuit.

FIG. 14 shows a time sequence diagram of using synchronous transmissionand store-and-forward for multi-path data transmission.

EMBODIMENTS OF THE INVENTION

The invention will be described in more detail with reference to thedrawings.

FIG. 3 shows a diagram of the invention for TDM concentrated switchingwith high-speed serial line. The clock circuit 101 of the center switchnetwork board 10 provides synchronous and clock signal, which can bedistributed by point-to-point mode or bus mode, to service boards 11.Between the TDM switching circuit 102 and the service boards 11 there isa high-speed serial line 13 for data transmission with point-to-pointmode.

FIG. 4 shows a TDM switching structure with TDM bridge connector for theinvention. Data, clock and sync signals of the TDM switching circuit 102are all connected to the TDM bridge connector 14. Aftermultiplexed/de-multiplexed, the TDM data from the TDM switching circuitare transmitted by the TDM bridge connector 14 through the high-speedserial line 13 on the backplane.

The TDM bridge connector 14 includes: a TDM high-speed serialtransmitting adaptive circuit connected with the data signal of the TDMswitching circuit on the one end and with the high-speed serial line atthe backplane on the another end, which receives multi-path TDM datatransmitted by the TDM switching circuit and sends them to thehigh-speed serial lines after multiplexing or interleaving and adapting;a high-speed serial receiving adaptive circuit connected with thehigh-speed serial lines on the one end and with the data signal of theTDM switching circuit on the other end, which receives serial datatransmitted by the high-speed serial line and sends them to the TDMswitching circuit after adapting and de-multiplexing or de-interleaving;and a clock control circuit connected with the clock and sync signals ofthe TDM switching circuit, which generates clock and sync signals.

FIG. 5 shows an embodiment of the TDM bridge connector 14. The TDMhigh-speed serial transmitting adaptive circuit includes: a TDMreceiving interface 141, which is connected with the data signal of theTDM switching circuit to receive the multi-path TDM data; astore-and-forward circuit 142, which converts the received multi-pathTDM data into one-path serial data; and a high-speed serial transmittinginterface 143, which is connected with the high-speed serial line 13 onthe backplane to make adaptation for the serial data and send them tothe high-speed serial line. The high-speed serial receiving adaptivecircuit includes: a high-speed serial interface 144, which is connectedwith the high-speed serial line 13 and receives the high-speed serialdata; a store-and-forward circuit 145, which converts the receivedserial data into multi-path TDM data; and a TDM transmitting interface146, which is connected with the TDM switching circuit to send themulti-path TDM data.

The clock control circuit 140 is connected with the clock and syncsignals of the TDM switching circuit and provides the clock signal tothe TDM high-speed serial transmitting adaptive circuit and the TDMhigh-speed serial receiving adaptive circuit.

FIG. 6 shows a block diagram of the center switch network board and aservice board with the FIG. 5 embodiment. Taking a frame as a unit, FIG.7 shows a time sequence for the multi-path data transmission. The centerswitch network board provides high-way (HW) sync and clock signals toevery service board, and the data is transmitted at the leading edge ofthe clock and sampled at the falling edge of the clock. It can be seenfrom the FIG. 7 that when the time T is guaranteed, reliability of datatransmission is guaranteed too and it is insensitive to the clock delay.Therefore, when transmission quality of the clock is satisfied thesystem requirement, distribution of the clock can be a point-to-pointmode or a bus mode.

Suppose the bandwidth of the high-speed serial line is 200 Mbps, whencombining six data signals and each of them being 32M, the bandwidth6×32=192 Mbps are occupied. So, there is enough redundancy forincreasing the traffic of each service board when using the high-speedserial line for transmission.

In FIG. 7, the Fri (i=1, 2, 3 . . . ) represents frames, it is n timesof the usual TDM period of a frame, wherein frequency of the frame canbe 8 k i.e. 8 k frame, n is a integer greater than zero; for example,the period of 8 k frame is 125 μs, the period of Fri can be 125 μs, 250μs or 375 μs etc. depending on the system design. The data transmissionprocedure on the high-speed serial line of FIG. 7 is as the followings:

1) During the first frame, i.e. FR1, the adaptive circuit of thehigh-speed serial line on the sending end assembles all HWs data in theFR1.

2) During second frame, i.e. FR2, the adaptive circuit of high-speedserial line on the sending end sends the FR1 data to the adaptivecircuit of high-speed serial line on the receiving end through thehigh-speed serial line.

3) During third frame, i.e. FR3, the adaptive circuit of the high-speedserial line on the receiving end de-multiplexes the received FR1 dataand sends to corresponding HW, respectively. FR1 data is transferred tothe TDM switching circuit of the destination board.

Really, the data transmission procedure mentioned above is a batchingtransmission procedure taking a frame as a unit.

The disadvantage of high-speed serial data transmission with a frame asa unit is that there is a two-frame fixed time delay. When usingmulti-frame multiplexing, i.e. taking n frames as a unit for every HW,or interleaved multiplexing, i.e. interleaving multiple HWs data inframes accordingly; the time delay will be n times of the single framemultiplexing. So, it is right in theory but inapplicable forimplementation.

FIG. 8 shows a time sequence for the multi-path data transmission whentaking a time-slot as a unit. The central switching board provides theframe synchronization signal and clock signal to HWs of every serviceboard; and the data is transmitted at leading edge of the clock andsampled at falling edge of the clock. It can be seen from FIG. 8 thatthe data transmission is reliable only requiring that the time T in FIG.8 to be guaranteed; and the data transmission is insensible to the clockdelay. Consequently, when transmission quality of the clock is satisfiedthe system requirement, the clock distribution can be a point-to-pointmode or a bus mode.

Suppose the bandwidth of the high-speed serial line is 200 Mbps, it cancombine five data signals and each of them is 32M, and the bandwidth5×32=160 Mbps are occupied. So, there is enough redundancy forincreasing the traffic of each service board when using the high-speedserial line for transmission.

In FIG. 8 the FRAME represents a frame, which is 8 k frame and has aperiod of 125 μs; the TS is a time-slot, which is an integer multiple ofthe usual TDM time-slot. For example, a 2M HW has a time-slot of eightclocks time, and the TS can be 16 clocks time or 24 clocks time etc.depending on the system design. The data transmission procedure on thehigh-speed serial line of FIG. 8 is as the following:

1) During the first time-slot, i.e. TS1, the adaptive circuit of thehigh-speed serial line on the sending end assembles all HWs data in theTS1.

2) During second time-slot, i.e. TS2, the adaptive circuit of high-speedserial line on the sending end sends the TS1 data to the adaptivecircuit of high-speed serial line on the receiving end through thehigh-speed serial line.

3) During third TS, i.e. TS3, the adaptive circuit of the high-speedserial line on the receiving end de-multiplexes the received TS1 dataand sends to corresponding HW, respectively. TS1 data is transferred tothe TDM switching circuit of the destination board.

Really, the data transmission procedure mentioned above is a batchingtransmission procedure taking a time-slot as a unit.

The disadvantage of the data transmission with a time-slot as a unit isthat each transfer will bring in a two time-slots fixed time delay, asshown in FIG. 8. Since the data pass the center switch network boardtwice, there are four time-slots fixed time delay, i.e. 4×Tts, whereinthe Tts is a time-slot period. As the data stream has a two time-slotsshift, data stream at the interface devices of the transmitter andreceiver of the boards has phase differences; it is necessary to have aphase adjusting circuit in front of the interface device to guaranteethat the phases are coincidence.

In the above multi-path TDM data transmission, themultiplexing/de-multiplexing is implemented at the store-and-forwardcircuit; it can also be implemented with aparallel-to-serial/serial-to-parallel circuit. FIG. 9 shows a TDM bridgeconnector implemented with the high-speed serial drivers: the serialtransmitter DS92LV1021 (151) and the serial receiver DS92LV1212 (152) ofthe National Semiconductor (NS) Company products.

FIG. 10 shows a block diagram of a center switch network board and aservice board for data transmission, where high-speed serial driversimplement the TDM bridge connector. When the multi-path datatransmission applies a synchronous multiplexing/de-multiplexing mode,the time sequence is shown in FIG. 11. The clock distribution can be apoint-to-point mode or a bus mode when transmission quality of clocksatisfies the system requirement. The clock circuit 101 on the centerswitch network board 10 provides to every service board the HW framesynchronous signal and HW clock signal, and data is transmitted at theleading edge and sampled at the falling edge of the HW clock signal. Itcan be seen from FIGS. 10 and 11, the multiple frequency circuit 16generates n multiple HW clock (n is a integer greater than 0). On thetransmitting end, the high-speed serial driver 15 samples the HWs dataand sends them to the high-speed serial line 13 at the leading edge ofthe multiple frequency clock; and on the receiving end, the TDMswitching circuit samples the data outputted from the high-speed serialdriver 15 at the falling edge of the HW clock.

FIG. 11 shows a three multiple HW clock case. At the sending end, aftert1 duration when the TDM switching circuit sent the HW data, thehigh-speed serial driver samples data at the leading edge of themultiple frequency clock and sends them to the high-speed serial line;and at the receiving end, the TDM switching circuit samples data at thefalling edge of the HW clock and there is t2 duration in between. Thedisadvantage of the synchronous multiplexing/de-multiplexing mode isthat the huge capacity of the high-speed serial line cannot be usedthoroughly. At present the point-to-point high-speed serial line canhave gigabits rate, but TDM transmission capacity of each high-speedserial line is limited by parallel number of high-speed driver.

FIG. 12 shows a block diagram of a center switch network board and aservice board for multi-path data transmission with synchronoustransmission and store-and-forward circuit; the time sequence is shownin FIG. 14. In this diagram, suppose the TDM clock is 32 MHz, thecentral control board 10 provides the TDM frame synchronizing signal andthe TDM clock signal to every service board 11; the data is transmittedat the leading edge and sampled at the falling edge of the TDM clock.

In FIG. 12, multiple-paths TDM data are transmitted parallel to thehigh-speed serial driver 15, i.e. multiple TDM data lines are connectedwith the parallel data lines of the high-speed serial driver 15; clockof the high-speed serial driver at transmitting end is provided by theTDM switching circuit and the high-speed serial driver at receiving endoutputs clock signal to the TDM switching circuit. The TDM switchingcircuit can distribute clock signals with point-to-point mode or busmode.

Suppose that the high-speed serial driver has 10 parallel data lines,then its transmission capacity is 32×10=320 Mbps, i.e. it can combine 10data signals with 32 Mbps. Therefore, with high-speed serial line, thereis enough extended redundancy for increasing service traffic at everyservice board.

In FIG. 14, the Fri (i=1, 2, 3 . . . ) represents frames, which is 8 kframe and has a period of 125 μs. The data transmission procedure on thehigh-speed serial line of FIG. 14 is shown in the following:

1) During first frame, i.e. FR1, the TDM switching circuit attransmitting end transmits data at the leading edge of the clock; andthe parallel data lines of the high-speed serial driver sample data atthe falling edge of the clock and sends them to the high-speed serialline. The high-speed serial line transmits 8×n bits in one clock periodand 8×n×4096 bits in a frame period.

2) During second frame, i.e. FR2, the high-speed serial driver of thereceiving end receives synchronously the FR1 data on the high-speed lineat the falling edge of the clock and sends synchronously to thestore-and-forward circuit 17 at the receiving end at the falling edge ofthe clock.

3) During third frame, i.e. FR3, the store-and-forward circuit 17 at thereceiving end sends the received FR1 data to the TDM switching circuitat the clock leading edge strictly according to the requirement of TDMframe time sequence, and the TDM switching circuit samples the data atthe falling edge.

The above three steps performs the FR1 TDM data transmission. Repeatthis procedure to perform the FR2, FR3 . . . data transmission.

FIG. 13 shows a block diagram of a center switch network board and aservice board for data transmission with synchronous transmissioncircuit and the store-and-forward circuit, adding multiple frequencyclock circuit 16. The clock of the high-speed serial driver can be ntimes of the TDM switching circuit clock, wherein n is integer greaterthan 0. The objective is to make the high-speed serial driver at thetransmitting end sample a TDM data earlier, but this is nonsense andwill increase cost and decrease reliability.

The disadvantage of this synchronous transmission and store-and-forwardmode is that there is a two-frames fixed time delay, as shown in FIG.14. When using the center switch network board to implement TDMconcentrated switching, first the data are sent from a service board tothe center switch network board, then forwarded to the interface board;this will cause a four frames fixed time delay, i.e. 4×T_(fr), whereinthe T_(fr) represents time period of one frame. When using multi-framemultiplexing, i.e. taking multi-frame as a unit for every HW, orinterleaved multiplexing, i.e. interleaving multiple HWs data in framesaccordingly; the time delay will be n times of the single framemultiplexing. So, it is inapplicable from the technology point of view.

In summary, the four embodiments can be compared in the following:

1) In the capacity aspect, the multi-path data transmission modes takinga frame as a unit or a time-slot as a unit can bring capacity of thehigh-speed serial driver into full play and have biggest capacity, butwith higher cost; the synchronous transmission and store-and-forwardmode can bring the parallel ports capacity of the high-speed serialdriver into full play and have moderate capacity and cost; thesynchronous multiplexing/de-multiplexing mode has smaller capacity andlittle cost.

2) In the time sequence aspect, the multi-path data transmission modestaking a frame as a unit or a time-slot as a unit and the synchronoustransmission and store-and-forward mode are insensitive to the clockdelay, but the synchronous multiplexing/de-multiplexing mode is moresensitive to the clock delay.

The high-speed serial line used in this invention includes not only thetransmitting and receiving lines but also the TDM frame synchronoussignal lines and clock lines. Signals on the high-speed serial line aredifferential signals.

The invention proposes a method for data transmission with thehigh-speed serial line on the backplane; and the method greatlyincreases the transmission capacity and looses the requirement of clocksynchronization; with making use of the advantages of high-speed serialsignals, the system reliability is increased greatly. The method has thefollowing effects:

1) It is insensitive to the clock delay; in the traditional TDM datatransmission on the backplane, the clock delay brings an unsymmetricalavailable transmission time and therefore brings an unreliable problemin the system. In the invention, above problems are solved.

2) It can provide a large capacity. High-speed serial line bringsqualitative change on TDM data transmission capacity. At present thepoint-to-point high-speed serial line can have more than one Gigabitsrate, and each high-speed line can transfer TDM data with several Mbpsbandwidth.

3) The high-speed serial line are all differential line, so they havegood suppression ratio for common-mode interference and better EMIcharacteristic, which can guarantee data integrity during high speedtransmission.

4) At present, the communication system is transited from the narrowbandto wideband and the wideband system uses high-speed serial line on thebackplane with great capacity for data packets transmission, so usinghigh-speed serial line on the backplane is coincidence with thetechnical development trend.

The method for data transmission with high-speed serial line based onbackplane has been described in detail, but it is not limited in theembodiments mentioned above. Any revision or equivalent replacementwithin the spirit and scope of the invention should be covered by thescope of the Claims.

1. A method for multi-path TDM data transmission comprising: applying aplurality of high-speed serial lines to connect a center switch networkboard with a plurality of service boards respectively, wherein thecenter switch network board provides a sync signal and a clock signalto, and exchanges TDM data with, each of the plurality of service boardsvia a respective one of the high-speed serial lines; obtaining, by thecenter switch network board, multi-path TDM data according to the syncsignal and the clock signal, multiplexing, by the center switch networkboard, the multi-path TDM data and transmitting the TDM data multiplexedin batch to the plurality of service boards via the plurality ofhigh-speed serial lines; receiving, by the plurality of service boards,the TDM data multiplexed, and de-multiplexing the TDM data multiplexedto the multi-path TDM data according to the sync signal and the clocksignal; wherein said obtaining multi-path TDM data according to the syncsignal and the clock signal, multiplexing the multi-path TDM data andtransmitting the TDM data multiplexed in batch to the plurality ofservice boards via the plurality of high-speed serial lines comprises:at a first frame, obtaining all High Ways data transmitted in the firstframe; at a second frame, transmitting the High Ways data obtained inthe first frame to the receiving side via the plurality of high-speedserial lines; wherein said receiving the TDM data multiplexed andde-multiplexing the TDM data multiplexed to the multi-path TDM dataaccording to the sync signal and the clock signal comprises at a thirdframe, receiving the High Ways data obtained in the first frame andde-multiplexing the High Ways data to respective High Way.
 2. A methodfor multi-path TDM data transmission comprising: applying a plurality ofhigh-speed serial lines to connect a center switch network board with aplurality of service boards respectively, wherein the center switchnetwork board provides a sync signal and a clock signal to, andexchanges TDM data with, each of the plurality of service boards via arespective one of the high-speed serial lines; obtaining, by the centerswitch network board, multi-path TDM data according to the sync signaland the clock signal, multiplexing, by the center switch network board,the multi-path TDM data and transmitting the TDM data multiplexed inbatch to the plurality of service boards via the plurality of high-speedserial lines; receiving, by the plurality of service boards, the TDMdata multiplexed, and de-multiplexing the TDM data multiplexed to themulti-path TDM data according to the sync signal and the clock signal;wherein said obtaining multi-path TDM data according to the sync signaland the clock signal, multiplexing the multi-path TDM data andtransmitting the TDM data multiplexed in batch to the plurality ofservice boards via the plurality of high-speed serial lines comprises:at a first slot, obtaining all High Ways data transmitted in the firstslot; at a second slot, transmitting the High Ways data obtained in thefirst slot to the receiving side via the plurality of high-speed seriallines; wherein said receiving the TDM data multiplexed andde-multiplexing the TDM data multiplexed to the multi-path TDM dataaccording to the sync signal and the clock signal, comprises at a thirdslot, receiving the High Ways data obtained in the first slot andde-multiplexing the High Ways data to respective High Way.
 3. The methodaccording to claim 1, wherein said obtaining multi-path TDM data,multiplexing the multi-path TDM data and transmitting the TDM datamultiplexed in batch according to the sync signal and the clock signalcomprises: at a leading edge of a multiple frequency clock, sampling allHigh Ways data, multiplexing the High Ways data and sending the all HighWays data multiplexed via the plurality of high-speed serial lines, andwherein said receiving the TDM data multiplexed comprises: at a fallingedge of the multiple frequency clock, receiving all the High Ways datavia the plurality of high-speed serial lines; wherein the multiplefrequency clock is an n multiple of a TDM clock that is used for thetransmitting and receiving, and n is an integer greater than zero. 4.The method according to claim 3, wherein multiplexing the High Ways datacomprises: converting the High Ways data from parallel to serial by ahigh-speed serial driver, and then sending the converted High Ways datato the plurality of high-speed serial lines; at receiving side, thehigh-speed serial driver synchronously receiving the converted High Waysdata, making serial-to-parallel conversion, and sampling each path ofTDM data according to the sync signal.
 5. The method according to claim1, wherein the sync signal and the clock signal are transmitted from thecenter switch network board to each of the plurality of service boardsby a point-to-point mode or a bus mode.
 6. A TDM bridge connector formulti-path TDM data transmission comprising: a TDM high-speed serialtransmitting adaptive circuit, connected with a TDM switching circuitand a plurality of high-speed serial lines, wherein the plurality ofhigh-speed serial lines are respectively connected with a plurality ofservice boards, the TDM high-speed serial transmitting adaptive circuitis adapted to receive multi-path TDM data from said TDM switchingcircuit, multiplex the multi-path TDM data and send the TDM datamultiplexed to of the plurality of service boards via the plurality ofhigh-speed serial lines according to a sync signal and a clock signalreceived from a clock circuit of a center switch network board; a TDMhigh-speed serial receiving adaptive circuit, connected with theplurality of high-speed serial lines and the TDM switching circuit,receive serial data sent from the plurality of high-speed serial lines,and convert the serial data to the multi-path TDM data and send themulti-path TDM data to the TDM switching circuit according to the syncsignal and the clock signal; and a clock control circuit, configured toreceive the sync signal and the clock signal from the clock circuit ofthe center switch network board and provide the clock signal and thesync signal to the TDM high-speed serial transmitting adaptive circuitand the TDM high-speed serial receiving adaptive circuit; wherein theTDM high-speed serial transmitting adaptive circuit comprises: a TDMreceiving interface, configured to connect to the TDM switching circuitand receive the multi-path TDM data transmitted by the TDM switchingcircuit; a first store-and-forward circuit, configured to convert themulti-path TDM data received by the TDM receiving interface to one pathserial data by performing the steps of: at a first frame, obtaining allHigh Ways data transmitted in the first frame; and at a second frame,transmitting the High Ways data obtained in the first frame to thereceiving side via the plurality of high-speed serial lines; and ahigh-speed serial transmitting interface, configured to connect with thehigh-speed serial lines and send the serial data to the high-speedserial lines; wherein the TDM high-speed serial receiving adaptivecircuit further comprises: a high-speed serial receiving interface,configured to connect with the high-speed serial lines and receiveserial data transmitted by the high-speed serial lines; a secondstore-and-forward circuit, configured to convert the received serialdata to multi-path TDM data; and a TDM transmitting interface,configured to connect with the TDM switching circuit and send themulti-path TDM data to the TDM switching circuit.
 7. A TDM bridgeconnector for multi-path TDM data transmission comprising: a TDMhigh-speed serial transmitting adaptive circuit, connected with a TDMswitching circuit and a plurality of high-speed serial lines, whereinthe plurality of high-speed serial lines are respectively connected witha plurality of service boards, the TDM high-speed serial transmittingadaptive circuit is adapted to receive multi-path TDM data from said TDMswitching circuit, multiplex the multi-path TDM data and send the TDMdata multiplexed to the plurality of service boards via the plurality ofhigh-speed serial lines according to a sync signal and a clock signalreceived from a clock circuit of a center switch network board; a TDMhigh-speed serial receiving adaptive circuit, connected with theplurality of high-speed serial lines and the TDM switching circuit,receive serial data sent from the plurality of high-speed serial lines,and convert the serial data to the multi-path TDM data and send themulti-path TDM data to the TDM switching circuit according to the syncsignal and the clock signal; and a clock control circuit, configured toreceive the sync signal and the clock signal from the clock circuit ofthe center switch network board and provide the clock signal and thesync signal to the TDM high-speed serial transmitting adaptive circuitand the TDM high-speed serial receiving adaptive circuit; wherein theTDM high-speed serial transmitting adaptive circuit comprises: a TDMreceiving interface, configured to connect with the TDM switchingcircuit and receive the multi-path TDM data transmitted by the TDMswitching circuit; a parallel-to-serial circuit, configured to convertthe received multi-path TDM data to one path serial data by performingthe steps of: at a first slot, obtaining all High Ways data transmittedin the first slot; and at a second slot, transmitting the High Ways dataobtained in the first slot to the receiving side via the plurality ofhigh-speed serial lines; and a high-speed serial transmitting interface,configured to connect with the plurality of high-speed serial lines andsend serial data to the plurality of high-speed serial lines afteradapting; wherein the TDM high-speed serial receiving adaptive circuitcomprises: a high-speed serial receiving interface, configured toconnect with the plurality of high-speed serial lines and receive serialdata transmitted by the plurality of high-speed serial lines; aserial-to-parallel circuit, configured to convert received serial datato multi-path TDM data; and a TDM transmitting interface, configured toconnect with the TDM switching circuit and send TDM data to the TDMswitching circuit.
 8. The TDM bridge connector according to claim 7,wherein the high-speed serial transmitting adaptive circuit is ahigh-speed serial driver; the high-speed serial receiving adaptivecircuit is a high-speed serial driver.
 9. The TDM bridge connectoraccording to claim 7, wherein the high-speed serial transmittingadaptive circuit further comprises a clock multiple frequency circuitconfigured to multiply the TDM switching circuit clock signal andprovide a multiple frequency as a high-speed serial transmission clocksignal; the high-speed serial receiving adaptive circuit furthercomprises a clock multiple frequency circuit configured to multiply TDMswitching circuit clock signal and provide a multiple frequency as ahigh-speed serial receiving clock signal.
 10. The TDM bridge connectoraccording to claim 8, said high-speed serial receiving adaptive circuitfurther comprises a store-and-forward circuit connecting with thehigh-speed serial driver.
 11. The TDM bridge connector according toclaim 10, wherein the high-speed serial transmitting adaptive circuitfurther comprises a clock multiple frequency circuit configured tomultiply the TDM switching circuit clock signal and provide a multiplefrequency as a high-speed serial transmitting clock signal.
 12. The TDMbridge connector according to claim 7, wherein the plurality ofhigh-speed serial lines comprise downward transmission lines from thecenter switch network board to the service boards and upwardtransmission lines from the service boards to the center switch networkboard.
 13. The TDM bridge connector according to claim 7, wherein theplurality of high-speed serial lines comprise a TDM data transmissionline, a TDM data receiving line, a TDM frame sync line and a clock line.14. The method according to claim 2, wherein said obtaining multi-pathTDM data, multiplexing the multi-path TDM data and transmitting the TDMdata multiplexed in batch according to the sync signal and the clocksignal comprises: at a leading edge of a multiple frequency clock,sampling all High Ways data, multiplexing the High Ways data and sendingthe all High Ways data multiplexed via the plurality of high-speedserial lines, and wherein said receiving the TDM data multiplexedcomprises: at a falling edge of the multiple frequency clock, receivingall the High Ways data via the plurality of high-speed serial lines;wherein the multiple frequency clock is an n multiple of a TDM clockthat is used for the transmitting and receiving, and n is an integergreater than zero.
 15. The method according to claim 14, whereinmultiplexing the High Ways data comprises: converting the High Ways datafrom parallel to serial by a high-speed serial driver, and then sendingthe converted High Ways data to the plurality of high-speed seriallines; at receiving side, the high-speed serial driver synchronouslyreceiving the converted High Ways data, making serial-to-parallelconversion, and sampling each path of TDM data according to the syncsignal.
 16. The method according to claim 2, wherein the sync signal andthe clock signal are transmitted from the center switch network board toeach of the plurality of service boards by a point-to-point mode or abus mode.